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www.fairchildsemi.com ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/20/11 AN-9738 design guideline on 150w power supply for led street lighting design using fl7930b and fan7621s introduction this application note describes a 150w rating desig n guideline for led street lighting. the application design consists of crm pfc and llc src with high power fac tor and high power conversion efficiency using fl7930b and fan7621s. to verify the validity of the application board and scheme, a demonstration board 150w (103v/1.46a) acdc converter was implemented and its results are presented in this application note. in crm active p fc, the most popular topology is a boost converter. this is because boost converters can have continuous input current that can be manipulated with peak current mode control techn iques to force peak current to track changes in line volt age. the fan7930b is an active power factor correction (pfc) controller for boost pfc applications that operate in critical conduction mode (crm). since it was first introduce d in early 1990s, llcsrc (series resonant converter) ha s became a most popular topology because of its outst anding performance in areas such as the output regulation of switching frequency, zvs capability for entire load range, low turnoff current, small resonant components usi ng the integrated transformer, zero current switching (zcs ), and no reverse recovery loss on secondary rectifier. figur e 1 shows the typical application circuit, with the crm pfc c onverter in the front end and the llc src dcdc converter in the back end. fl7930b and fan7621s achieve high efficie ncy with medium power for 150w rating applications wher e crm and llc src operation with a twostage shows be st performance. crm boost pfc converters can achieve b etter efficiency with light and medium power rating than continuous conduction mode (ccm) boost pfc converters. these benefits result from the eliminat ion of the reverserecovery losses of the boost diode and zero current switching (zcs). the llc src dcdc converter achiev es higher efficiency than the conventional hard switch ing converter. the fl7930b provides a controlled ontim e to regulate the output dc voltage and achieves natural power factor correction. the fan7621s includes a highsid e gate driver circuit, accurate currentcontrolled oscilla tor, frequency limit circuit, softstart, and builtin protections. the highside gate drive circuit has a commonmode noise cancellation capability, which guarantees stable op eration with excellent noise immunity. using zero voltage switching (zvs) dramatically reduces switching loss es and significantly improves efficiency. zvs also reduces switching noise noticeably, which allows a smallsi zed electromagnetic interference (emi) filter. figure 1. typical application circuit
an9738 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/20/11 2 1. basic operation of bcm pfc pre-regulator the most widely used operation modes for the boost converter are continuous conduction mode (ccm) and boundary conduction mode (bcm). these two descripti ve names refer to the current flowing through the ener gy storage inductor of the boost converter, as depicte d in figure 2. as the names indicate, the inductor curre nt in ccm is continuous; while in bcm, the new switching period is initiated when the inductor current retur ns to zero, which is at the boundary of continuous conduction a nd discontinuous conduction operations. even though th e bcm operation has higher rms current in the inductor an d switching devices, it allows better switching condi tion for the mosfet and the diode. as shown in figure 2, the diode reverse recovery is eliminated and a fastrec overy diode is not needed. the mosfet is also turned on w ith zero current, which reduces the switching loss. v in i l i d v out i ds l line filter v line figure 2. ccm vs. bcm control the fundamental idea of bcm pfc is that the inducto r current starts from zero in each switching period, as shown in figure 3. when the power transistor of the boost converter is turned on for a fixed time, the peak i nductor current is proportional to the input voltage. since the current waveform is triangular; the average value in each s witching period is proportional to the input voltage. in a s inusoidal input voltage, the input current of the converter f ollows the input voltage waveform with very high accuracy and draws a sinusoidal input current from the source. this be havior makes the boost converter in bcm operation an ideal candidate for power factor correction. a side effect of bcm is that the boost converter ru ns with variable switching frequency that depends primarily on the selected output voltage, the instantaneous value of the input voltage, the boost inductor value, and the output p ower delivered to the load. the operating frequency chan ges as the input current follows the sinusoidal input volt age waveform, as shown in figure 3. the lowest frequenc y occurs at the peak of sinusoidal line voltage. figure 3. operation waveforms of bcm pfc the voltagesecond balance equation for the inducto r is: ( ) off in out on in t )t( v v t )t( v ? ? = ? (1) where v in(t) is the rectified line voltage and v out is the output voltage. the switching frequency of bcm boost pfc converter is: ( ) out line pk , in out on out in out on off on sw v t f sin v v t v )t( v v t t t f ? ? ? ? ? = ? ? = + = 2 1 1 1 (2) where v in,pk is the amplitude of the line voltage and f line is the line frequency. figure 4 shows how the mosfet ontime and switching frequency change as output power decreases. when th e load decreases, as shown in the right side of figure 4, the peak inductor current diminishes with reduced mosfet on time and, therefore, the switching frequency increases. since this can cause severe switching losses at lightload con dition and toohigh switching frequency operation may occur at startup, the maximum switching frequency of fl7930b is limited to 300khz.
an9738 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/20/11 3 i l v gs average of input current f sw t figure 4. frequency variation of bcm pfc since the design of the filter and inductor for a b cm pfc converter with variable switching frequency should be at minimum frequency condition, it is worthwhile to ex amine how the minimum frequency of bcm pfc converter changes with operating conditions. 2. consideration of llc resonant converter the attempt to obtain everincreasing power density in switchedmode power supplies has been limited by th e size of passive components. operation at higher frequenc ies considerably reduces the size of passive components , such as transformers and filters; however, switching los ses have been an obstacle to highfrequency operation. to re duce switching losses and allow highfrequency operation , resonant switching techniques have been developed. these techniques process power in a sinusoidal manner and the switching devices are softly commutated. therefore, the switching losses and noise can be dramatically redu ced. among various kinds of resonant converters, the sim plest and most popular is the lc series resonant converter, w here the rectifierload network is placed in series with the lc resonant network, as depicted in figure 5. in this configura tion, the resonant network and the load act as a voltage divi der. by changing the frequency of driving voltage v d , the impedance of the resonant network changes. the input voltage is split between this impedance and the reflected load. sinc e it is a voltage divider, the dc gain of a lc series resonan t converter is always <1. at lightload condition, the impedanc e of the load is large compared to the impedance of the reso nant network; all the input voltage is imposed on the lo ad. this makes it difficult to regulate the output at light load. theoretically, frequency should be infinite to regu late the output at no load. figure 5. half-bridge, lc series resonant converter to overcome the limitation of series resonant conve rters, the llc resonant converter has been proposed. the llc resonant converter is a modified lc series resonant converter implemented by placing a shunt inductor a cross the transformer primary winding, as depicted in fig ure 6. when this topology was first presented, it did not receive much attention due to the counterintuitive concept that increasing the circulating current in the primary s ide with a shunt inductor can be beneficial to circuit operati on. however, it can be very effective in improving effi ciency for highinput voltage applications where the switc hing loss is more dominant than the conduction loss. in most practical designs, this shunt inductor is r ealized using the magnetizing inductance of the transformer . the circuit diagram of llc resonant converter looks muc h the same as the lc series resonant converter: the only difference is the value of the magnetizing inductor . while the series resonant converter has a magnetizing ind uctance larger than the lc series resonant inductor (l r ), the magnetizing inductance in an llc resonant converter is just 3~8 times l r , which is usually implemented by introducing an air gap in the transformer. figure 6. half-bridge llc resonant converter an llc resonant converter has many advantages over a series resonant converter. it can regulate the outp ut over wide line and load variations with a relatively sma ll variation of switching frequency. it can achieve ze ro voltage switching (zvs) over the entire operating range. al l essential parasitic elements; including the junctio n capacitances of all semiconductor devices, the leak age inductance, and magnetizing inductance of the trans former; are utilized to achieve soft switching.
an9738 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/20/11 4 this application note presents design consideration s for an llc resonant halfbridge converter employing fairch ilds fan7621s. it includes explanation of the llc resona nt converter operation principles, designing the trans former and resonant network, and selecting the components. the stepbystep design procedure, explained with a des ign example, helps design the llc resonant converter. 0 shows a simplified schematic of a halfbridge llc resonan t converter, where l m is the magnetizing inductance that acts as a shunt inductor, l r is the series resonant inductor, and c r is the resonant capacitor. figure 8 illustrates the typical waveforms of the llc resonant converter. it is assu med that the operation frequency is the same as the resonanc e frequency, determined by the resonance between l r and c r . since the magnetizing inductor is relatively small, a considerable amount of magnetizing current ( i m ) exists, which freewheels in the primary side without being involved in the power transfer. the primaryside cu rrent ( i p ) is the sum of the magnetizing current and the secon daryside current referred to the primary. in general, the llc resonant topology consists of t he three stages shown in 0; squarewave generator, resonant network, and rectifier network. the squarewave generator produces a squarewave voltage, v d , by driving switches q 1 and q 2 alternately with 50% duty cycle for each switch. a small dead t ime is usually introduced between the consecutive transitions. the squarewave generator stage can be built as a fullbridge or halfbridge type. the resonant network consists of a capacitor, leaka ge inductances, and the magnetizing inductance of the transformer. the resonant network filters the highe r harmonic currents. essentially, only sinusoidal cur rent is allowed to flow through the resonant network eve n though a squarewave voltage is applied. the curren t ( i p ) lags the voltage applied to the resonant network (that is, the fundamental component of the squarew ave voltage ( v d ) applied to the halfbridge totem pole), which allows the mosfets to be turned on with zero voltage. as shown in figure 8, the mosfet turns on while the voltage across the mosfet is zero by flowing current through the antiparallel diode. the rectifier network produces dc voltage by rectifying the ac current with rectifier diodes and a capacitor. the rectifier network can be implemented as a fullwave bridge or a centertapped configuration with capacitive output filter. figure 7. schematic of half-bridge llc resonant converter i p i ds1 v d i m v in i d v gs2 v gs1 figure 8. typical waveforms of half-bridge llc resonant converter the filtering action of the resonant network allows the use of the fundamental approximation to obtain the volt age gain of the resonant converter, which assumes that only the fundamental component of the squarewave voltage in put to the resonant network contributes to the power trans fer to the output. because the rectifier circuit in the second ary side acts as an impedance transformer, the equivalent lo ad resistance is different from actual load resistance . figure 9 shows how this equivalent load resistance is derive d. the primaryside circuit is replaced by a sinusoidal cu rrent source, i ac , and a square wave of voltage, v ri , appears at the input to the rectifier. since the average of | i ac | is the output current, i o , i ac , is obtained as: sin( ) 2 o ac i i t ? = (3)
an9738 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/20/11 5 and v ri is given as: sin( ) 0 sin( ) 0 ri o ri o v v if t v v if t = + > = ? < (4) where v o is the output voltage. the fundamental component of v ri is given as: 4 sin( ) f o ri v v t = (5) since harmonic components of v ri are not involved in the power transfer, ac equivalent load resistance can b e calculated by dividing v ri f by i ac as: 2 2 8 8 f o ri ac o ac o v v r r i i = = = (6) considering the transformer turns ratio (n=n p /n s ), the equivalent load resistance shown in the primary sid e is obtained as: 2 2 8 ac o n r r = (7) by using the equivalent load resistance, the ac equ ivalent circuit is obtained, as illustrated in figure 10, w here v d f and v ro f are the fundamental components of the driving volt age, v d and reflected output voltage, v ro ( nv ri ), respectively. pk ac i 4 sin( ) f o ri v v wt = ) sin( 2 wt i i o ac ? = figure 9. derivation of equivalent load resistance r ac v o l m l r c r r o v in v d f (nv ri f ) l m l r c r r ac n p :n s v d + - - + v ri n=n p /n s 2 2 8 ac o n r r = + - v ro f figure 10. ac equivalent circuit for llc resonant converter with the equivalent load resistance obtained in equ ation 7, the characteristics of the llc resonant converter c an be derived. using the ac equivalent circuit of figure 10, the voltage gain, m , is obtained as: 2 2 2 2 2 4 sin( ) 2 4 sin( ) 2 ( ) ( 1) ( 1) ( 1)( 1) o f f ro ri o f f in d d in o p o o n v t v n v n v m v v v v t m j m q ? ? ? = = = = ? = ? + ? ? (8) where: 2 2 8 , , 1 1 1 , , p p m r ac o r r o p r ac r r p r l n l l l r r m l l q c r l c l c = + = = = = = as can be seen in equation (8), there are two reson ant frequencies. one is determined by l r and c r , while the other is determined by l p and c r . equation (8) shows the gain is unity at resonant fr equency ( o ), regardless of the load variation, which is given as: 2 2 2 ( 1) 2 1 p o o in o p m n v m at v ? ? ? = = = = ? (9) the gain of equation (8) is plotted in figure 11 fo r different q values with m=3, f o =100khz, and f p =57khz. as observed in figure 11, the llc resonant converter shows gain characteristics that are almost independent of the load when the switching frequency is around the resonant freq uency, f o . this is a distinct advantage of llctype resonant c onverter over the conventional series resonant converter. th erefore, it is natural to operate the converter around the r esonant frequency to minimize the switching frequency varia tion.
an9738 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/20/11 6 the operating range of the llc resonant converter i s limited by the peak gain (attainable maximum gain), which is indicated with q in figure 11. note that the p eak voltage gain does not occur at f o or f p . the peak gain frequency, where the peak gain is obtained, exists between f p and f o , as shown in figure 11. as q decreases (as load decreases), the peak gain frequency moves to f p and higher peak gain is obtained. meanwhile, as q increases (a s load increases), the peak gain frequency moves to f o and the peak gain drops; the fullload condition should be worst case for the resonant network design. 1 2 p p r f l c = / r r ac l c q r = @ 1 o f m = 1 2 o r r f l c = figure 11. typical gain curves of llc resonant converter ( m =3) 3. design considerations this design procedure uses the schematic in figure 1 as a reference. a 150w street lighting application with universal input range is selected as a design example. the de sign specifications are: line voltage range: 85v a ~277v ac (50hz) output of converter: 103v/1.46a (150w) pfc output voltage: 430v overall efficiency: 90% (pfc: 95%, llc: 95%) 3.1 pfc section [ step-1] define system specification line frequency range ( v line,min and v line,max ) line frequency ( f line ) outputvoltage ( v out ) output load current ( i out ) output power ( p out = v out i out ) estimated efficiency ( ) to calculate the maximum input power, it is necessa ry to estimate the power conversion efficiency. at univer sal input range, efficiency is recommended at 0.9; 0.93~0.95 is recommended when input voltage is high. when input voltage is set at the minimum, input current become s the maximum to deliver the same power compared at high line. maximum boost inductor current can be detected at t he minimum line voltage and at its peak. inductor curr ent can be divided into two categories; rising current when the mosfet is on and output diode current when the mosf et is off, as shown in figure 12. figure 12. inductor and input current because switching frequency is much higher than lin e frequency, input current can be assumed to be const ant during a switching period, as shown in figure 133. figure 13. inductor and input current with the estimated efficiency, figure 12 and figure 13, inductor current peak (i l,pk ) , maximum input current (i in,max ), and input root mean square (rms) current (i in,maxrms ) are given as: ] a [ v p i min , line out pk , l ? ? ? = 2 4 (10) ] a [ / i i pk ,l max , in 2 = (11) ] a [ / i i max , in maxrms , in 2 = (12) (design example) input voltage range is universal input, output load is 465ma, and estimated efficiency is s elected as 0.9. 9.0 465 , 430 50 277 , 85 , , = = = = = = ma i v v hz f v v v v out out line ac max line ac min line a a i i a a i i a a v v p i max in maxrms in pk l max in min line out pk l 613 .2 2 696 .3 2 696 .3 2 392 .7 2 392 .7 85 2 9.0 465 .0 430 4 2 4 , , , , , , = = = = = = = ? ? ? ? = ? ? ? =
an9738 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/20/11 7 [step-2] boost inductor design the boost inductor value is determined by the outpu t power and the minimum switching frequency. the minimum switching frequency must be higher than the maximum audible frequency band of 20khz. minimum frequency near 20khz can decrease switching loss with the cost of increased inductor size and line filter size. tooh igh minimum frequency may increase the switching loss a nd make the system respond to noise. selecting in the range of about 30~60khz is a common choice; 40~50khz is recommended with fl7930b. the minimum switching frequency may appear at minim um input voltage or maximum input voltage, depending o n the output voltage level. when pfc output voltage is le ss than 430v, minimum switching appears at the maximum inpu t voltage (see fairchild application note an6086) . inductance is obtained using the minimum switching frequency: ( ) ] h [ v v v p f v l line out line out min , sw line ? ?? ? ? ?? ? ? + ? ? ? ? = 2 2 1 4 2 2 (13) where l is boost inductance and f sw,min is the minimum switching frequency. the maximum ontime needed to carry peak inductor current is calculated as: [s] v 2 i l t min line, pk l, max on, ? ? = (14) once inductance and the maximum inductor current ar e calculated, the turn number of the boost inductor s hould be determined considering the core saturation. the min imum number of turns is given as: ] turns [ b ] mm [ a ] h [ l i n e pk ,l boost ? ? 2 (15) where a e is the crosssectional area of the core and b is the maximum flux swing of the core in tesla. b should be set below the saturation flux density. figure 14 shows the typical bh characteristics of a ferrite core from tdk (pc45). since the saturation flux den sity ( b ) decreases as the temperature increases, the high temperature characteristics should be considered. rms inductor current (i l,rms ) and current density of the coil (i l,density ) can be given as: ] a [ i i pk ,l rms ,l 6 = (16) ] mm / a [ n d i i wire wire rms ,l density ,l 2 2 2 ? ?? ? ?? ? ? = (17) where d wire is the diameter of winding wire and n wire is the number of strands of winding wire. when selecting wire diameter and strands; current d ensity, window area (a w , refer to figure 14) of the selected core, and fill factor need to be considered. the winding sequence of the boost inductor is relatively simple compared to a dc dc converter, so fill factor can be assumed about 0 .2~0.3. layers cause the skin effect and proximity effect i n the coil, so real current density may be higher than expected . figure 14. typical b-h curves of ferrite core figure 15. a e and a w (design example) since the output voltage is 430v, the minimum frequency occurs at highline (277v ac ) and full load condition. assuming the efficiency is 90% and selecting the minimum frequency as 50khz, the induc tor value is obtained as: ( ) ( ) ] h [ . . v v v p f v l line out line out min , sw line = ? ?? ? ? ?? ? ? ? ? + ? ? ? ? ? = ? ?? ? ? ?? ? ? + ? ? ? ? = 2 307 277 2 430 277 2 1 200 10 50 4 277 2 9 0 2 2 1 4 2 3 2 2 assuming eer3019n core (pl7, a e =137mm 2 ) is used and setting b as 0.3t, the primary winding should be: ] t[ 55 3.0 137 307 392 .7 b ] mm [ a ] h [l i n 2 e pk ,l boost = ? ? = ? ? the number of turns (n boost ) of the boost inductor is determined as 55 turns. when 0.10mm diameter and 50strand wire is used, rm s current of inductor coil and current density are:
an9738 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/20/11 8 ] a [ . . i i pk ,l rms ,l 017 3 6 392 7 6 = = = ( ) ] mm /a [ . / . . n d i i wire wire rms ,l density ,l 2 2 2 68 7 50 2 1 0 017 3 2 = ? ? = ? ?? ? ?? ? ? = [step-3] inductor auxiliary winding design figure 16 shows the application circuit of the near by zcd pin from auxiliary winding. figure 16. application circuit of zcd pin the first role of zcd winding is detecting the zero current point of the boost inductor. once the boost inducto r current becomes zero, the effective capacitance (c eff ) at the mosfet drain pin and the boost inductor resonate together. to minimize the constant turnon time deterioration and turnon loss, the gate is turned on again when the drain source voltage of the mosfet (v ds ) reaches the valley point shown in figure 17. when i nput voltage is lower than half of the boosted output vo ltage, zero voltage switching (zvs) is possible if mosfet turn on is triggered at valley point. figure 17. zcd detection waveforms auxiliary winding must give enough energy to trigge r zcd threshold to detect zero current. minimum auxiliary winding turns are given as: ] turns [ v v n v . n max , line out boost aux 2 5 1 ? ? (18) where 1.5v is the positive threshold of the zcd pin . to guarantee stable operation, it is recommended to add 2~3 turns to the auxiliary winding turns calculated in equation (18) . however, too many auxiliary winding turns raise t he negative clamping loss at high line and positive cl amping loss at low line. (design example) 55 turns are selected as boost inductor turns and auxiliary winding turns are calculated as : ] turns [ . . v v n v . n max , line out boost aux 15 2 277 2 430 55 5 1 2 5 1 = ? ? ? = ? ? choice should be around 4~5 turns after adding 2~3 turns. [step-4] zcd circuit design if a transition time when v auxiliary drops from 1.4v to 0v is ignored from figure 17, the necessary additional delay by the external resistor and capacitor is one quarter of the resonant period. the time constant made by zcd resi stor and capacitor should be the same as one quarter of the resonant period: 4 2 l c c r eff zcd zcd ? = ? (19) where c eff is the effective capacitance at the mosfet drain pin; c zcd is the external capacitance at the zcd pin; and r zcd is the external resistance at the zcd pin. the second role of r zcd is the current limit of the internal negative clamp circuit when auxiliary voltage drops to negative due to mosfet turn on. zcd voltage is clam ped 0.65v and minimum r zcd can be given as: ] [ ma v . v n n r max , line boost aux zcd ? ?? ? ? ?? ? ? 3 65 0 2 (20) where 3ma is the clamping capability of the zcd pin . the calculation result of equation (20) is normally higher than 15k . if 20k is assumed as r zcd , calculated c zcd from equation (19) is around 10pf when the other components are assumed as conventional values used in the field. because most ic pins have several pf of para sitic capacitance, c zcd can be eliminated when r zcd is higher than 30k . however, a small capacitor would be helpful when auxiliary winding suffers from operating noise . the pfc control loop has two conflicting goals: out put voltage regulation and making the input current sha pe the same as input voltage. if the control loop reacts t o regulate output voltage smoothly, as shown in figure 18, con trol
an9738 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/20/11 9 voltage varies widely with the input voltage variat ion. input current acts to the control loop and sinusoidal inp ut current shape cannot be attained. this is the reason contro l response of most pfc topologies is very slow and turnon tim e over ac period is kept constant. this is also the reason output voltage ripple is made by input and output power relationship, not by controlloop performance. figure 18. input current deterioration by fast cont rol if ontime is controlled constantly over one ac per iod, the inductor current peak follows ac input voltage shap e and achieves good power factor. offtime is basically i nductor current reset time due to boundary mode and is dete rmined by the input and output voltage difference. when in put voltage is at its peak, the voltage difference betw een input and output voltage is small and long turnoff time is necessary. when input voltage is near zero, turnof f time is short, as shown in figure 19 and figure 20. though inductor current drops to zero, the minor delay is explained above. the delay can be assumed as fixed when ac is at line peak and zero. near ac line peak, the inductor current decreasing slope is slow and inductor current slope is also slow during the zcd delay. the amount of negative c urrent is not much higher than the inductor current peak. near the ac line zero, inductor current decreasing slope is very high and the amount of negative current is higher than p ositive inductor current peak because input voltage is almo st zero. figure 19. inductor current at ac voltage peak figure 20. inductor current at ac voltage zero negative inductor current creates zerocurrent dist ortion and degrades the power factor. improve this by extendin g turn on time at the ac line input near the zero cross. negative auxiliary winding voltage, when the mosfet is turned on, is linearly proportional to the input vo ltage. sourcing current generated by the internal negative clamping circuit is also proportional to sinusoidal input voltage. that current is detected internally and ad ded to the internal sawtooth generator, as shown in figure 21. figure 21. zcd current and sawtooth generator when the ac input voltage is almost zero, no negati ve current is generated from inside, but sourcing curr ent when input voltage is high is used to raise the sawtooth generator slope and turnon time is shorter. as a result, tur non time when ac voltage is zero is longer compared to ac vo ltage, in peaks shown in figure 22.
an9738 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/20/11 10 figure 22. thd improvement the current that comes from the zcd pin, when auxil iary voltage is negative, depends on r zcd . the second role of r zcd is also related to improving the total harmonic distortion (thd). the third role of r zcd is making the maximum turnon time adjustment. depending on sourcing current from the zcd pin, the maximum ontime varies as in figure 23. figure 23. maximum on-time variation vs. i zcd with the aid of i zcd , an internal sawtooth generator slope is changed and turnon time varies as shown in figure 24. figure 24. internal sawtooth wave slope variation r zcd also influences control range. because fl7930b doesnt detect input voltage, voltagemode control value is determined by the turnon time to deliver the neede d current to boost output voltage. when input voltage increas es, control voltage decreases rapidly. for example, if input voltage doubles, control voltage drops to one quart er. making control voltage maximum when input voltage i s low and at full load is necessary to use the whole cont rol range for the rest of the input voltage conditions. match ing maximum turnon time needed at low line is calculat ed in equation (14) and turnon time adjustment by r zcd guarantees use of the full control range. r zcd for control range optimization is obtained as: ] [ n ma . n v t t s r boost aux min , line max , on max , on zcd ? ? ? ? ? 469 0 2 28 1 (21) where: t on,max is calculated by equation (14) ; t on,max1 is maximum ontime programming 1; n boost is the winding turns of boost inductor; and n aux is the auxiliary winding turns. r zcd calculated by equation (20) is normally lower than the value calculated in equation (21). to guarantee the needed turn ontime for the boost inductor to deliver rate d power, the r zcd from equation (20) is normally not suitable. r zcd should be higher than the result of equation (21) w hen output voltage drops as a result of low line voltag e. when input voltage is high and load is light, not m uch input current is needed and control voltage of v comp touches switching stop level, such as if fl7930b is 1v. however, in some applications, a pfc block is needed to operate normally at light load. to compensate control range correctly, input voltage sensing is necessary, such as with fairchilds interleaved pfc controller fan9612, or special care on sawtooth generator is necessary. to guarant ee enough control range at high line, clamping output voltage lower than rated on the minimum input condition can help. (design example) minimum r zcd for clamping capability is calculated as: = ?? ? ?? ? ? ? = ? ?? ? ? ?? ? ? k . ma v . ma v . v n n r max , line boost aux zcd 9 18 3 65 0 277 2 34 5 3 65 0 2 minimum r zcd for control range is calculated as: = ? ? ? ? ? = ? ? ? ? ? k . ma . s . s s n ma . n v t t s r boost aux min , line max , on max , on zcd 97 20 55 469 0 5 85 2 9 10 42 28 469 0 2 28 1 a choice close to the value calculated by the contr ol range is recommended. 39k is chosen in this case.
an9738 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/20/11 11 [step-5] output capacitor selection the output voltage ripple should be considered when selecting the output capacitor. figure 25 shows the line frequency ripple on the output voltage. with a give n specification of output ripple, the condition for t he output capacitor is obtained as: ] f [ v f i c ripple , out line out out ? ? 2 (22) where v out,ripple is the peaktopeak output voltage ripple specification. the output voltage ripple caused by the esr of the electrolytic capacitor is not as serious as other p ower converters because output voltage is high and load current is small. since too much ripple on the output voltage may cause premature ovp during normal operation, the pe akto peak ripple specification should be smaller than 15 % of the nominal output voltage. the holdup time should also be considered when determining the output capacitor as: ( ) ]f[ v v . v t p c min , out ripple , out out hold out out 2 2 5 0 2 ? ? ? ? ? (23) where t hold is the required holdup time and v out,min is the minimum output voltage during holdup time. t i diode i diode,ave i diode,ave =i out (1cos(4p.f l .t)) v out i out v out,ripple = i out 2p.f l .c out figure 25. output voltage ripple the voltage rating of capacitor can be obtained as: ] v [ v v v v out ref max ,p ov cout , st ? = (24) where v ovp,max and v ref are the maximum tolerance specifications of overvoltage protection triggerin g voltage and reference voltage at error amplifier, respectiv ely. (design example) with the ripple specification of 8v pp , the capacitor should be: ] f [ . v f i c ripple , out line out o = ? ? = ? ? 185 8 50 2 465 0 2 since minimum allowable output voltage during one c ycle line (20ms) dropouts is 330v, the capacitor should be: ( ) ( ) ] f [ . v v . v t p c min , out ripple , out out hold out o = ? ? ? ? ? = ? ? ? ? ? 110 330 8 5 0 430 10 20 200 2 5 0 2 2 2 3 2 2 to meet both conditions, the output capacitor must be larger than 140 f. a 240 f capacitor is selected for the output capacitor. the voltage stress of selected capacitor is calcula ted as: ] v [ . . . v v v v out ref max , ovp cout , st 5 469 430 500 2 730 2 = ? = ? = [step-6] mosfet and diode selection selecting the mosfet and diode requires extensive knowledge and calculation regarding loss mechanisms and gets more complicated if proper selection of a heat sink is added. sometimes the loss calculation itself is bas ed on assumptions that may be far from reality. refer to industry resources regarding these topics. this note shows t he voltage rating and switching loss calculations base d on a linear approximation. the voltage stress of the mosfet is obtained as: ] v [ v v v v v dout , drop out ref max ,p ov q, st + ? = (25) where v drop,dout is the maximum forwardvoltage drop of output diode. after the mosfet is turned off, the output diode tu rns on and a large output electrolytic capacitance is show n at the drain pin; thus a drain voltage clamping circuit th at is necessary on other topologies is not necessary in p fc. during the turnoff transient, boost inductor curre nt changes the path from mosfet to output diode. before the ou tput diode turns on; a minor voltage peak can be shown a t drain pin, which is proportional to mosfet turnoff speed . mosfet loss can be divided into three parts: conduc tion loss, turnoff loss, and discharge loss. boundary m ode guarantees zero current switching (zcs) of the mosf et when turned on, so turnon loss is negligible. the mosfet rms current and conduction loss are obtained as: ] a [ v v i i out line pk ,l rms ,q ? ? ? ? = 9 2 4 6 1 (26) ( ) ] w [ r i p on , ds rms , q con , q ? = 2 (27)
an9738 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/20/11 12 where i q,rms is the rms value of mosfet current, p q,con is the conduction loss caused by mosfet current, and r ds,on is the on resistance of the mosfet. on resistance is described as static on resistance and varies depending on junction temperature. that vari ation information is normally supplied as a graph in the datasheet and may vary by manufacturer. when calculating conduction loss, generally multiply three by the r ds,on for more accurate estimation. the precise turnoff loss calculation is difficult because of the nonlinear characteristics of mosfet turnoff. w hen piecewise linear current and voltage of mosfet during turnoff and inductive load are assumed, mosfet tur noff loss is obtained as: ] w [ f t i v p sw off l out swoff ,q ? ? ? ? = 2 1 (28) where t off is the turnoff time and f sw is the switching frequency. boundary mode pfc inductor current and switching frequency vary at every switching moment. rms induc tor current and average switching frequency over one ac period can be used instead of instantaneous values. individual loss portions are changed according to t he input voltage; maximum conduction loss appears at low lin e because of high input current; and maximum switchin g off loss appears at high line because of the high switc hing frequency. the resulting loss is always lower than the summation of the two losses calculated above. capacitive discharge loss made by effective capacit ance shown at drain and source, which includes mosfet c oss , an externally added capacitor to reduce dv/dt and p arasitic capacitance shown at drain pin, is also dissipated at mosfet. that loss is calculated as: ( ) ] w [ f v c c c p sw out par ext oss dischg ,q ? ? + + = 2 2 1 (29) where: c oss is the output capacitance of mosfet; c ext is an externally added capacitance at drain and so urce of mosfet; and c par is the parasitic capacitance shown at drain pin. because the c oss is a function of the drain and source voltage, it is necessary to refer to graph data sho wing the relationship between c oss and voltage. estimate the total power dissipation of mosfet as t he sum of three losses: ] w [ p p p p dischg ,q swoff ,q con ,q q + + = (30) diode voltage stress is the same as the output capa citor stress calculated in equation (24). the average diode current and power loss are obtain ed as: ] a [ i i out ave , dout = (31) ] w [ i v p ave , dout dout , drop dout ? = (32) where v drop,dout is the forward voltage drop of diode. (design example) internal reference at the feedback pin is 2.5v and maximum tolerance of ovp trigger voltage i s 2.730v. if fairchilds fdpf17n60nt mosfet and ffpf08h60s diode are selected, v d,for is 2.1v at 8a, 25c, maximum r ds,on is 0.34 at drain current is 17a, and maximum c oss is 32pf at drainsource voltage is 480v. ] v [ . . . . v v v v v diode , drop out ref max ,p ov q, st 6 471 1 2 430 50 2 73 2 = + ? = + ? = ( ) ( ) ] w [ . . . r v v i p on , ds out line pk ,l con ,q 23 2 34 0 430 9 85 2 4 6 1 392 7 9 2 4 6 1 2 2 = ? ? ? ?? ? ? ? ?? ? ? ? ? ? = ? ? ? ?? ? ? ? ?? ? ? ? ? ? = ] w [ . ) . / k ( ns . f t i v p sw off l out swoff , q 755 1 8 0 50 50 613 2 430 2 1 2 1 = ? ? ? ? = ? ? ? ? = ( ) ] w [ . ) . / k ( p f v c c c p sw out par ext oss dischg , q 184 0 8 0 50 430 32 2 1 2 1 2 2 = ? ? ? = ? ? + + ? = diode average current and forwardvoltage drop loss as: ] a [ . . . i i out ave , dout 56 0 9 0 5 0 = = = ] w [ . . . i v p ave , dout for , dout loss , dout 46 1 56 0 1 2 = ? = ? = [step-7] determine current-sense resistor it is typical to set pulsebypulse current limit l evel a little higher than the maximum inductor current calculated by equation (10). for 10% margin, the currentsensing resistor is selected as: ] [ . i v r pk ,l lim , cs cs ? = 11 (33) once resistance is calculated, its power loss at lo w line is calculated as: ] w [ r i p cs rms ,q rcs ? = 2 (34) power rating of the sensing resistor is recommended a twice the power rating calculated in equation (34).
an9738 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/20/11 13 (design example) maximum inductor current is 4.889a and sensing resistor is calculated as: ] [ . . . . . i v r pk ind lim , cs cs = ? = ? = 098 0 11 392 7 8 0 11 choosing 0.1 as r cs , power loss is calculated as: ] w [ . . . r i p cs rms ,q loss , rcs 58 0 098 0 436 2 2 2 = ? = ? = recommended power rating of sensing resistor is 1.1 9w. [step-8] design compensation network the boost pfc power stage can be modeled as shown i n figure 26 mosfet and diode can be changed to lossf ree resistor model and then modeled as a voltagecontro lled current source supplying rc network. figure 26. small signal modeling of the power stage by averaging the diode current during the half line cycle, the lowfrequency behavior of the voltage controlle d current source of figure 26 is obtained as: ] a [ l v v v k i line ut o line saw ave , dout 2 4 2 ? ? = (35) where: l is the boost inductance; v out is the output voltage; and k saw is the internal gain of sawtooth generator (that o f fl7930b is 8.496 10 6 ). then the lowfrequency, smallsignal, controltoou tput transfer function is obtained as: ( ) p ut o l line saw comp out f s l v r v k v v + ? ? ? = 2 1 1 4 2 (36) where out l p c r f ? = 2 2 and r l is the output load resistance in a given load condition. figure 27 and figure 28 show the variation of the c ontrol tooutput transfer function for different input vol tages and different loads. since dc gain and crossover freque ncy increase as input voltage increases, and dc gain in creases as load decreases, high input voltage and light loa d is the worst condition for feedback loop design. figure 27. control-to-output transfer function for different input voltages figure 28. control-to-output transfer function for different loads proportional and integration (pi) control with high frequency pole is typically used for compensation, as shown in figure 29. the compensation zero (f cz ) introduces phase boost, while the highfrequency compensation pole ( f cp ) attenuates the switching ripple. the transfer function of the compensation network i s obtained as: cp cz i out comp f s f s s f v v + + ? = 2 1 2 1 2 (37)
an9738 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/20/11 14 where ( ) ? ?? ? ? ?? ? + ? ? ? = ? ? = + ? ? = hf , comp lf , comp hf , comp lf , comp comp cp lf , comp comp cz hf , comp lf , comp out i c c c c r f c r f c c mho v . f 2 1 2 1 2 115 5 2 if c comp,lf is much larger than c comp,hf , f i and f cp can be simplified as: ] hz [ c r f ] hz [ c mho v . f hf , comp comp cp lf , comp out i ? ? ? ? ? ? 2 1 2 115 5 2 (38) mho 115 g m = figure 29. compensation network the feedback resistor is chosen to scale down the o utput voltage to meet the internal reference voltage: v . v r r r out fb fb fb 5 2 2 1 1 = ? + (39) typically, high r fb1 is used to reduce power consumption and c fb can be added to raise the noise immunity. the maximum c fb currently used is several nano farads. adding a capacitor at the feedback loop introduces a pole as: ( ) ] hz [ c r c r // r f fb fb fb fb fb fp ? ? ? ? ? = 2 2 1 2 1 2 1 (40) where ( ) 2 1 2 1 2 1 fb fb fb fb fb fb r r r r r // r + ? = . though r fb1 is high, pole frequency made by the synthesized total resistance and several nano farad s is several kilo hertz and rarely affects controlloop response the procedure to design the feedback loop is: a. determine the crossover frequency (f c ) around 1/10 ~ 1/5 of line frequency. since the controltooutput transfer function of the power stage has 20db/dec slope and 90 o phase at the crossover frequency; it is required to place the zero of the compensation netw ork (f cz ) around the crossover frequency so 45 phase margin is obtained. the capacitor c comp,lf is determined as: ( ) ( ) ]f[ f c l v mho . v k c c out out line saw lf , comp 2 2 2 2 2 115 5 2 ? ? ? ? ? (41) to place the compensation zero at the crossover frequency, the compensation resistor is obtained as : ] [ c f r lf , comp c comp ? ? = 2 1 (42) b. place this compensator highfrequency pole (f cp ) at least a decade higher than f c to ensure that it does not interfere with the phase margin of the voltage regulation loop at its crossover frequency. it shou ld also be sufficiently lower than the switching frequency of the converter for noise to be effectively attenuate d. the capacitor c comp,hf is determined as: ] [ r f c comp cp hf , comp ? ? = 2 1 (43)
an9738 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/20/11 15 (design example) if r fb1 is 11.7m , then r fb2 is: = ? = ? = k r v v v r fb out fb 68 10 7. 11 5.2 430 5.2 5.2 5.2 6 1 2 choosing the crossover frequency (control bandwidth ) at 15hz, c comp,lf is obtained as: ( ) ( ) ( ) ( ) nf f c l v mho v k c c out out line saw lf comp 823 15 2 10 240 10 199 430 2 10 115 5.2 230 10 496 .8 2 2 115 5.2 2 6 6 2 6 2 6 2 2 2 , = ? ? ? ? = ? ? ? ? ? ? ? ? ? actual c comp,lf is determined as 1000nf since it is the closest value among the offtheshelf capacitors. r comp is obtained as: = ? ? = ? ? = ? k c f r lf comp c comp 8. 12 10 823 15 2 1 2 1 9 , selecting the highfrequency pole as 150hz, c comp,hf is obtained as: nf r f c comp cp hf comp 82 10 8. 12 150 2 1 2 1 3 , = ? ? = ? ? = these components result in a control loop with a ba ndwidth of 19.5hz and phase margin of 45.6 . the actual bandwidth is a little larger than the asymptotic design. [step-9] line filter capacitor selection it is typical to use small bypass capacitors across the bridge rectifier output stage to filter the switching curr ent ripple, as shown in figure 30. since the impedance of the line filter inductor at line frequency is negligible compared t o the impedance of the capacitors, the line frequency beh avior of the line filter stage can be modeled, as shown in f igure 30. even though the bypass capacitors absorb switching ripple current, they also generate circulating capacitor c urrent, which leads the line voltage by 90 o , as shown in figure 31. the circulating current through the capacitor is ad ded to the load current and generates displacement between lin e voltage and current. the displacement angle is given by: ( ) ? ?? ? ? ?? ? ? ? ? ? = ? out eq line line p c f v tan 2 2 1 (44) where c eq is the equivalent capacitance that appears across the ac line (c eq =c f1 +c f2 +c hf ). the resultant displacement factor is: ( ) = cos df (45) since the displacement factor is related to power f actor, the capacitors in the line filter stage should be selec ted carefully. with a given minimum displacement factor (df min ) at fullload condition, the allowable effective i nput capacitance is obtained as: ( ) ( ) ( ) ] f [ df cos tan f v p c mn line line out ea 1 2 2 ? ? ? ? ? < (46) one way to determine if the input capacitor is too high or pfc control routine has problems is to check power factor (pf) and total harmonic distortion (thd). pf is the degree to which input energy is effectively transferred to the load by the multiplication of displacement factor and th d that is input current shape deterioration ratio. pfc contro l loop rarely has no relation to displacement factor and i nput capacitor rarely has no impact on the input current shape. if pf is low (high is preferable), but thd is quite go od (low is preferable), it can be concluded that input capacit ance is too high and pfc controller is fine. (design example) assuming the minimum displacement factor at full load is 0.98, the equivalent input c apacitance is obtained as: ( ) ( ) ( ) ( ) ( ) ( ) f . . cos tan . df cos tan f v p c mn line line out ea = ? ? ? ? < ? ? ? ? < ? ? 6 1 98 0 50 2 277 9 0 200 2 1 2 1 2 thus, the sum of the capacitors on the input side s hould be smaller than 2.0f.
an9738 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/20/11 16 figure 30. equivalent circuit of line filter stage figure 31. line current displacement 3.2 llc src section in this section, a design procedure is presented us ing the schematic in figure 1 as a reference. an integrated transformer with center tap, secondary side is used and input is supplied from power factor correction (pfc) pre regulator. a dcdc converter with 150w/103v output is selected as a design example. the design specificat ions are: nominal input voltage: 400v dc (output of pfc stage) output: 103v/1.46a (150w) holdup time requirement: 30ms (50hz line freq.) dc link capacitor of pfc output: 240f [step-10] define system specifications estimated efficiency ( e ff ): the power conversion efficiency must be estimated to calculate the maxim um input power with a given maximum output power. if n o reference data is available, use e ff = 0.88~0.92 for low voltage output applications and e ff = 0.92~0.96 for high voltage output applications. with the estimated eff iciency, the maximum input power is given as: o in ff p p e = (47) input voltage range ( v in min and v in max ): the maximum input voltage would be the nominal pfc output volta ge as: max . in o pfc v v = (48) even though the input voltage is regulated as const ant by pfc preregulator, it drops during the holdup time . the minimum input voltage considering the holdup time requirement is given as: min 2 . 2 in hu in o pfc dl p t v v c = ? (49) where v o.pfc is the nominal pfc output voltage, t hu is a holdup time, and c dl is the dc link bulk capacitor. (design example) assuming the efficiency is 92%, w e p p ff o in 163 92 .0 150 = = = dl hu in pfc o in c t p v v 2 2 . min ? = v 379 10 240 10 30 163 2 430 6 3 2 = ? ? ? = ? ? [step-11] determine maximum and minimum voltage gains of the resonant network as discussed in the previous section, it is typical to operate the llc resonant converter around the resonant freq uency ( f o ) to minimize switching frequency variation. since the input of the llc resonant converter is supplied fro m pfc output voltage, the converter should be designed to operate at f o for the nominal pfc output voltage. as observed in equation (9), the gain at f o is a function of m ( m=l p /l r ). the gain at f o is determined by choosing that value of m . while a higher peak gain can be obtained with a small m value, too small m value results in poor coupling of the transformer and deteriorates the efficiency. it is typical to set m to be 3~7, which results in a voltage gain of 1.1~ 1.2 at the resonant frequency ( f o ). with the chosen m value, the voltage gain for the nominal pfc output voltage is obtained as:
an9738 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/20/11 17 min 1 m m m = ? @f=f o (50) which would be the minimum gain because the nominal pfc output voltage is the maximum input voltage ( v in max ). the maximum voltage gain is given as: max max min min in in v m m v = (51) (design example) the ratio ( m ) between l p and l r is chosen as 5. the minimum and maximum gains are obtained as: 12 .1 1 5 5 1 2 max min = ? = ? = = m m v v m in ro 31 .1 12 .1 341 400 min min max max = ? = = m v v m in in f o 1.12 1 m m m = = ? f s gain (m) m min m max for v in min for v in max 1.31 1.12 peak gain (available maximum gain) ( v o.pfc ) figure 32. maximum gain / minimum gain [step-12] determine the transformer turns ratio (n=n p /n s ) with the minimum gain (m min ) obtained in step11, the transformer turns ratio is given as: max min 2( ) p in s o f n v n m n v v = = ? + (52) where v f is the secondaryside rectifier diode voltage drop . (design example) assuming v f is 0.9v: 06 .2 12 .1 )9.0 103 (2 430 ) (2 min max = ? + = ? + = = m v v v n n n f o in s p [step-13] calculate equivalent load resistance with the transformer turns ratio obtained from equa tion (52), the equivalent load resistance is obtained as : 2 2 2 8 o ac o n v r p = (53) (design example) = ? ? ? = + = 217 150 9. 103 93 .1 8 ) ( 8 2 2 2 2 2 2 o f o ac p v v n r [step-14] design the resonant network with the m value chosen in step11, read the proper q value from the peak gain curves in figure 33 that a llows enough peak gain. considering the load transient an d stable zerovoltageswitching (zvs) operation, 10~20% marg in should be introduced on the maximum gain when determining the peak gain. once the q value is determined, the resonant parameters are obtained as: 1 2 r o ac c q f r = ? ? (54) 2 1 (2 ) r o r l f c = (55) p r l m l = ? (56) (design example) as calculated in step11, the maximum voltage gain ( m max ) for the minimum input voltage ( v in min ) is 1.31. with 15% margin, a peak gain of 1.51 is required. m has been chosen as 5 in step11 and q is obtained as 0.38 from the peak gain curves in figure 33. by selecting the res onant frequency as 100khz, the resonant components are determined as: nf . ac r o f q r c 19 217 3 10 100 38 0 2 1 2 1 = ? ? ? = ? ? = h ) ( c ) f ( l r o r = ? = = ? 133 10 19 10 100 2 1 2 1 9 2 3 2 h l m l r p = ? = 665 figure 33. resonant network design using the peak gain (attainable maximum gain) curve for m =5
an9738 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/20/11 18 [step-15] design the transformer the worst case for the transformer design is the mi nimum switching frequency condition, which occurs at the minimum input voltage and fullload condition. to o btain the minimum switching frequency, plot the gain curv e using gain equation (8) and read the minimum switching frequency. the minimum number of turns for the transformer primaryside is obtained as: min min ( ) 2 o f p s v e n v v n f m b a + = ? ? ? (57) where a e is the crosssectional area of the transformer core in m 2 and b is the maximum flux density swing in tesla, as shown in figure 34. if there is no refere nce data, use b =0.3~0.4 t. n (v o +v f )/m v n (v o +v f )/m v 1/(2 f s ) b v ri b figure 34. flux density swing choose the proper number of turns for the secondary side that results in primaryside turns larger than n p min as: min p s p n n n n = ? > (58) (design example) eer3542 core (a e =107mm 2 ) is selected for the transformer. from the gain curve of figure 35, the minimum switching frequency is obtained as 82khz. t he minimum primaryside turns of the transformer is gi ven as: e s f o p a b f v v n n ? ? + = 11 .1 2 ) ( min min turns 26 10 107 11 . 1 4 . 0 10 82 2 9. 103 93 .1 6 3 = ? ? ? = ? choose n s so that the resultant n p is larger than n p min : min min min min min min 37 19 93 .1 35 18 93 .1 33 17 93 .1 31 16 93 .1 29 15 93 .1 27 14 93 .1 p s p p s p p s p p s p p s p p s p n n n n n n n n n n n n n n n n n n n n n n n n > = = ? = > = = ? = > = = ? = > = = ? = < = = ? = < = = ? = figure 35. gain curve [step-16] transformer construction parameters l p and l r of the transformer were determined in step14. l p and l r can be measured in the primary side with the secondaryside winding open circuited and short circuited, respectively. since llc converter design requires a relatively large l r , a sectional bobbin is typically used, as shown in figure 36, to obtain the desired l r value. for a sectional bobbin, the number of turns and winding configuration are the major factors determining the value of l r , while the gap length of the core does not affect l r much. l p can be controlled by adjusting the gap length. tab le 1. shows measured l p and l r values with different gap lengths. a gap length of 0.05mm obtains values for l p and l r closest to the designed parameters. n p n s1 n s2 figure 36. sectional bobbin table 1. measured l p and l r with different gap lengths gap length l p l r 0.0mm 2,295h 123h 0.05mm 943h 122h 0.10mm 630h 118h 0.15mm 488h 117h 0.20mm 419h 115h 0.25mm 366h 114h
an9738 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/20/11 19 (design example) final resonant network design even though the integrated transformer approach in llc resonant converter design can implement the magneti c components in a single core and save one magnetic component, the value of l r is not easy to control in real transformer design. resonant network design sometim es requires iteration with a resultant l r value after the transformer is built. the resonant capacitor value is also changed since it should be selected among offthes helf capacitors. the final resonant network design is su mmarized in table 2. and the new gain curves are shown in fi gure 37. table 2. final resonant network design parameters parameters initial design final design l p 665h 691h l r 133h 122h c r 19nf 22nf f o 100khz 96khz m 5 5 q 0.38 0.3 m at f o 1.12 1.12 minimum frequency 75khz 74.4khz figure 37. gain curve of the final resonant network design [step-17] select the resonant capacitor when choosing the resonant capacitor, the current r ating should be considered because a considerable amount of current flows through the capacitor. the rms curren t through the resonant capacitor is given as: 2 2 1 ( ) [ ] [ ] 2 2 4 2 ( ) r rms o o f c ff o v p r i n v v i e n f m l l + ? + ? (59) the nominal voltage of the resonant capacitor in no rmal operation is given as: max 2 2 2 r rms nom in cr c o r v i v f c ? ? + ? ? ? (60) however, the resonant capacitor voltage increases h igher than this at overload condition or load transient. actual capacitor selection should be based on the overcur rent protection (ocp) trip point. with the ocp current, i ocp , the maximum resonant capacitor voltage is obtained as: max 2 2 r nom in ocp c o r v i v f c ? + ? ? ? (61) (design example) 2 2 ] ) ( 2 4 ) ( [ ] 2 2 [ 1 r p v o f o o ff rms c l l m f v v n n i e i r ? + + ? 2 ] 6 10 500 12 .1 3 10 96 2 4 )9.0 103 ( 93 .1 [ 2 ] 93 .1 2 2 4.1 [ 92 .0 1 ? ? ? ? + + ? ? = =1.12a the peak current in the primary side in normal oper ation is: a i i rms c peak c r r 58 .1 2 = ? = ocp level is set to 2.5a with 50% margin on i cr peak : r o rms c in nom c c f i v v r r ? ? ? ? + ? 2 2 2 max v 340 10 22 10 96 2 18 .1 2 2 430 9 3 = ? ? ? ? + = ? r o ocp in c c f i v v r ? ? ? + ? 2 2 max max v 3. 403 10 22 10 96 2 5.2 2 430 9 3 = ? ? ? + = ? a 630v rated lowesr film capacitor is selected for the resonant capacitor. [step-18] rectifier network design when the center tap winding is used in the transfor mer secondary side, the diode voltage stress is twice o f the output voltage expressed as: 2( ) d o f v v v = + (62) the rms value of the current flowing through each r ectifier diode is given as: 4 rms d o i i = (63)
an9738 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/20/11 20 meanwhile, the ripple current flowing through outpu t capacitor is given as: 2 2 2 8 ( ) 8 2 2 rms o co o o i i i i ? = ? = (64) the voltage ripple of the output capacitor is: 2 o o c v i r = ? (65) where r c is the effective series resistance (esr) of the output capacitor and the power dissipation is the o utput capacitor is: 2 . ( ) rms loss co co c p i r = ? (66) (design example) the voltage stress and current stress of the rectifier diode are: v v v v f o d 8. 207 )9.0 103 (2 ) (2 = + = + = a i i o rms d 14 .1 4 = = the 600v/8a ultrafast recovery diode is selected f or the rectifier, considering the voltage overshoot caused by the stray inductance. the rms current of the output capacitor is: a i i i i o o o rms c o 584 .0 8 8 ) 2 2 ( 2 2 2 = ? = ? = when two electrolytic capacitors with esr of 100m are used in parallel, the output voltage ripple is give n as: v r i v c o o 114 .0 ) 2 1.0 ( 46 .1 2 2 = ? ? = ? = the loss in electrolytic capacitors is: w r i p c rms c c loss o o 017 .0 05 .0 584 .0 ) ( 2 2 , = ? = ? = [step-19] control circuit configuration figure 38 shows the typical circuit configuration f or the rt pin of fan7621s, where the optocoupler transistor is connected to the rt pin to control the switching fr equency. the minimum switching frequency occurs when the opt o coupler transistor is fully tuned off, which is giv en as: min min 5.2 100( ) k f khz r = (67) assuming the saturation voltage of optocoupler tra nsistor is 0.2v, the maximum switching frequency is determined as: max min max 5.2 4.68 ( ) 100( ) k k f khz r r = + (68) figure 38. typical circuit configuration for rt pin softstart prevents excessive inrush current and ov ershoot of output voltage during startup, increases the voltag e gain of the resonant converter progressively. since the vol tage gain of the resonant converter is reversely proportional to the switching frequency, softstart is implemented by s weeping down the switching frequency from an initial high frequency ( f iss ) until the output voltage is established, as illustrated in figure 39. the softstart circuit is made by connecting rc series network on the rt pin as shown in figure 38. fan7621s also has an internal softstart for 3ms to reduce the current overshoot during the initial cycles, which adds 40khz to the initial frequency of the ex ternal softstart circuit, as shown in figure 39. the actu al initial frequency of the softstart is given as: min 5.2 5.2 ( ) 100 40 ( ) iss ss k k f khz r r = + + (69) it is typical to set the initial frequency of soft start ( f iss ) at 2~3 times of the resonant frequency ( f o ). the softstart time is determined by the rc time co nstant: ) c r ( ~ t ss ss ss ? = 4 3 (70) figure 39. frequency sweep of the soft-start
an9738 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/20/11 21 (design example) the minimum frequency is 75khz in step15. r min is determined as: = = k k f khz r 93 .6 2.5 100 min min considering the output voltage overshoot during tra nsient (10%) and the controllability of the feedback loop, the maximum frequency is set as 140khz. r max is determined as: ) 2.5 100 40 .1 ( 68 .4 min max r k khz f k r o ? = = ? = k k k khz khz k 88 .7 ) 93 .6 2.5 100 40 .1 96 ( 68 .4 setting the initial frequency of softstart as 250k hz (2.5 times of the resonant frequency), the softstart re sistor r ss is given as: ) 2.5 100 40 ( 2.5 min r k khz khz f k r iss ss ? ? = = ? ? = k k k khz khz khz k 85 .3 ) 93 .6 2.5 100 40 250 ( 2.5 [step-20] current sensing and protection fan7621s senses lowside mosfet drain current as a negative voltage, as shown in figure 40. and figure 41. halfwave sensing allows low power dissipation in t he sensing resistor, while fullwave sensing has less switching noise in the sensing signal. typically, an rc lowp ass filter is used to filter out the switching noise in the se nsing signal. the rc time constant of the lowpass filter should be 1/100~1/20 of the switching period. figure 40. half-wave sensing figure 41. full-wave sensing (design example) since the ocp level is determined as 2.5a in step17 and the ocp threshold voltage is 0 .6v, a sensing resistor of 0.24 is used. the rc time constant is set to 100ns (1/100 of switching period) with 1k ?resistor and 100pf capacitor. [step-21] voltage and current feedback power supplies for led lighting must be controlled by constant current (cc) mode as well as a constant vo ltage (cv) mode. because the forwardvoltage drop of led varies with the junction temperature and the curren t also increases greatly consequently, devices can be dama ged. figure 42 shows an example of a cc and cv mode feedback circuit for singleoutput led power supply . during normal operation, cc mode is dominant and th e cv control circuit does not activate as long as the fe edback voltage is lower than reference voltage, which mean s that cv control circuit only acts as ovp for abnormal mo des. (design example) the output voltage (v o ) is 103v in design target. v o is determined as: ) 1(5.2 fl fu o r r v + = set the upperside feedback resistance (r fu ) as 330k . r fl is determined as: = ? = ? = k k v r r o fu fl 2.8 )5.2 103 ( 330 5.2 )5.2 ( 5.2 the output current (i led ) is 1.46a in design target. assuming the sensing resistor (r sense ) of 0.1 and feedback resistor (r202) of 47k? are used, the input resistor r203 is determined as: 36 .0 202 ) ( 36 .0 202 203 r i r r v r led sense sense = = = = k k 19 36 . 0 47 ) 46 .1 1.0( figure 42. example of cc and cv feedback circuit
an9738 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/20/11 22 4. schematic of the evaluation board figure 43. evaluation board schematic rp38a 0.2 dp5 rs1m rp17 10 cp17 10uf/16v rp2 1m m3 fdpf7n60nz cp18 12n cp1 22nf/630v rp36 10k cp6 33uf/25v rp37 1k cp4 120uf/450v dp3 rs1m zdp2 mmsz5235 rp15 47k cs11 220nf c2 3.3n 0 rp10 33k m1 fcpf11n65 cs3 470nf lf2 10mh 1 2 3 4 rs2 1m u1 fan7930b vcc 8 gnd 6 inv 1 zcd 5 cs 4 out 7 ovp 2 comp 3 rp13 4.3m cp22 6.8uf/50v cp8 120uf/450v 0 cp20 0.68uf/630v rp33 0.1/5w cs4 470nf rp20 4.3m cs8 47uf dp4 ll4148 dp1 ffpf08h60s rs1 1m zdp1 mmsz5248 pfc rp1 390k rp18 4.7 rs3 1m rp30 10k cp15 1nf rp5 68k/2w cp5 120uf/450v fg j2 con2 1 2 q4 mmbt2222a dp6 ll4148 rp28 3 rp22 10 u4 mmbt2907a dp7 ll4148 rp35 3 rp34 10 u5 mmbt2907a 0 q2 mmbt2907a cs9 4.7nf cs10 4.7nf lf1 10mh 1 2 3 4 rp11 10k vdc cp21 33uf/25v cp9 0.1uf tm1 eer3019n 4 5 3 1 2 10 8 6 7 9 cp16 1nf rp3 4.3m cn1 con3 1 2 rp16 27 - + bd1 1 2 3 4 rp21 4.3m rp8 10k znr1 1 2 rp14 4.3m u3 mmbt2907a rp12 24k cp11 470pf q3 mmbt2222a cp2 33uf/25v rp4 4.3m rp7 0 cs7 47uf rp27 5.2k cs6 47uf pc1a ps2561 1 2 q1 mmbt2222a 0 0 0 0 0 vdc 0 rp29 75k rp31 75k 0 cs5 47uf 0 0 isense cp14 1uf fan7621s u2 fan7621s 1.hvcc 2.ctr 3.ho 6.a/r 8.rt 9.cs 10.sg 12.lvcc 14.lo 16.pg rp6 0 rp24 8.2k cp7 680p d1 ffpf20ua60dn cp10 1uf vaux cs1 47uf j1 con12 1 2 3 4 5 6 7 8 9 10 11 12 cs2 47uf d2 ffpf20ua60dn c1 100nf vled cp19 100p rp9 1m rp32 10k rp19 10 m2 fdpf7n60nz rp23 2k ds1 rs1m f1 fs101 rp25 2.7k pc1b ps2561 4 3 cp13 33uf/25v dp2 rs1m zdp3 mmsz5248 rp26 33k vfb tm2 eer3543 1 2 3 4 5 6 7 16 10 9 8 12 15 14 13 11 fb cs6 33uf/25v vaux rs56 47k cs25 220nf rs41 4.7k isense rs33 47k cs19 220nf vled u6a lm358/on + 3 2 v+ 8 v 4 out 1 ds2 ll4148 vfb u6b lm358/on + 5 6 v+ 8 v 4 out 7 ds3 ll4148 rs40 100k rs42 0.1 u7 tl431 vaux rs35 13k rs57 330k j6 con12 1 2 3 4 5 6 7 8 9 10 11 12 rs44 n.c r46 n.c rs55 120k rs49 1k rs59 8.2k
an9738 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/20/11 23 dimensions: 240 (w) 80 (h) [mm] figure 44. top view of evaluation board figure 45. bottom view of evaluation board 5. bill of materials item no. qty reference part reference description ( manufacturer) 1 1 bd1 600v/8a bridge diode (fairchild semiconduct or) 2 1 cn1 3pin connector 3 1 cp1 630v22nf film capacitor 4 5 cp2,cp6,cp13,cp21 33f/25v smd tantal capacitor 5 3 cp4,cp5,cp8 120f/450v electrolytic capacitor 6 1 cp7 680p/25v smd capacitor 2012 7 1 cp9 0.1f/25v smd capacitor 2012 8 2 cp10,cp14 1f/25v smd capacitor 2012 9 1 cp11 470pf/25v smd capacitor 2012 10 2 cp15,cp16 33f/25v smd capacitor 2012 11 1 cp17 10f/16v electrolytic capacitor 12 1 cp18 12nf/25v smd capacitor 2012 13 1 cp19 100pf/26v smd capacitor 2012 14 1 cp20 0.68f/630v film capacitor 15 1 cp22 100p/25v smd capacitor 2012 16 6 cs1,cs2,cs5,cs6,cs7,cs8 47f/200v electrolytic capacitor 17 2 cs3,cs4 470nf/400v film capacitor cs19,cs25 220nf/25v smd capacitor 2012
an9738 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/20/11 24 item no. qty reference part reference description ( manufacturer) 18 2 cs9,cs10 220p/400v ceramic capacitor 19 3 cs11 220nf/400v film capacitor 20 1 c1 100nf/50v smd capacitor 3216 21 1 c2 4.7f/400v ceramic capacitor 22 1 dp1 600v/8a hyperfast2 diode 23 4 ds1,dp2,dp3,dp5 1000v/1a fast rectifier diode 24 5 ds2,ds3,dp4,dp6,dp7 100v/200ma smd general pur pose diode 25 2 d1,d2 600v/20a ultrafast diode 26 1 f1 fs101 fuse 27 2 j1,j6 12pin connector 28 1 j2 2pin connector 29 2 lf1,lf2 10mh/2.3a commonmode filter 30 1 m1 650v/11a mosfet 31 2 m2,m3 600v/7a mosfet 32 1 pc1 photo copuler photo coupler 33 3 q1,q3,q4 40v/1a smd npn transitor 34 4 q2,u3,u4,u5 40v/200ma smd pnp transitor 35 1 rp1 390k/25v smd resistor 2012 36 5 rs1,rs2,rp2,rs3,rp9 1m/50v smd resistor 3216 37 6 rp3,rp4,rp13,rp14,rp20,rp21 4.3m/50v smd resistor 3216 38 1 rp5 68k/2w watt resistor 39 2 rp6,rp7 0/50v smd resistor 3216 40 5 rp8,rp11 10k/25v smd resistor 2012 rp30,rp32,rp36 10k/50v smd resistor 3216 41 2 rp10,rp26 33k/25v smd resistor 2012 42 1 rp12 24k/50v smd resistor 3216 43 3 rp15,rs33,rs56 47k/25v smd resistor 2012 44 1 rp16 2.7/25v smd resistor 2012 45 4 rp17,rp19 10/50v smd resistor 3216 rp22,rp34 10/25v smd resistor 2012 46 1 rp18 4.7/25v smd resistor 2012 47 1 rp23 10k/25v smd resistor 2012 48 2 rp24,rs59 8.2k/25v smd resistor 2012 49 1 rp25 1.8k/25v smd resistor 2012 50 1 rp27 5.1k/25v smd resistor 2012 51 2 rp28,rp35 3/25v smd resistor 2012 52 2 rp29,rp31 75k/50v smd resistor 3216 53 1 rp33 0.1/5w watt resistor 54 2 rp37,rs49 1k/50v smd resistor 3216 55 1 rp38a 0.1/1w watt resistor 56 1 rs35 13k/25v smd resistor 2012 57 1 rs40 100k/25v smd resistor 2012 58 1 rs41 4.7k/25v smd resistor 2013 59 1 rs42 0.1/2w watt resistor
an9738 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/20/11 25 item no. qty reference part reference description ( manufacturer) 60 2 rs44,r46 nc nc 61 1 rs55 120k/25v smd resistor 2012 62 1 rs57 330k/25v smd resistor 2012 63 1 tm1 eer3019n10 pfc inductor 64 1 tm2 eer354316 llc transformer 65 1 u1 fl7930b crm pfc controller 66 1 u2 fan7621s llc resonant controller 67 1 u6 lm358 opamp 68 1 u7 ka431 shunt regulator 69 2 zdp1,zdp3 mmsz5248 zener diode 18v 70 1 zdp2 mmsz5235 zener diode 6.8v 71 1 znr1 10d471 varistor 470v related datasheets fl7930b singlestage flyback and boundary mode pf c controller for lighting fan7621s controller for resonant half bridge fdpf17n60nt 600v nchannel mosfet, unifet?2 fdpf7n60nz 600v nchannel mosfet, unifet?2 author wonseok, kang power conversion korea senior system and application engineer wonseok.kang@fairchildsemi.com disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising ou t of the application or use of any product or circuit descri bed herein; neither does it convey any license unde r its patent rights, nor the rights of others. life support policy fairchilds products are not authorized for use as critical components in life support devices or syst ems without the express written approval of the preside nt of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or s ystems which, (a) are intended for surgical implant into the body , or (b) support or sustain life, or (c) whose failure to pe rform when properly used in accordance with instructions for u se provided in the labeling, can be reasonably expected to resu lt in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonabl y expected to cause the failure of the life support d evice or system, or to affect its safety or effectiveness.

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